US 12,068,288 B2
Semiconductor integrated circuit device and semiconductor package structure
Atsushi Okamoto, Yokohama (JP); Hirotaka Takeno, Yokohama (JP); and Wenzhen Wang, Yokohama (JP)
Assigned to SOCIONEXT INC., Kanagawa (JP)
Filed by SOCIONEXT INC., Kanagawa (JP)
Filed on Mar. 6, 2023, as Appl. No. 18/179,013.
Application 18/179,013 is a division of application No. 17/206,257, filed on Mar. 19, 2021, granted, now 11,626,386.
Application 17/206,257 is a continuation of application No. PCT/JP2019/036598, filed on Sep. 18, 2019.
Claims priority of application No. 2018-183553 (JP), filed on Sep. 28, 2018.
Prior Publication US 2023/0223381 A1, Jul. 13, 2023
Int. Cl. H01L 23/50 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H01L 27/088 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/50 (2013.01); H01L 23/5384 (2013.01); H01L 27/088 (2013.01)] 3 Claims
OG exemplary drawing
 
1. A semiconductor package structure, comprising:
a package substrate having a power supply external terminal provided on one surface; and
a semiconductor integrated circuit device mounted on the other surface of the package substrate,
wherein:
the semiconductor integrated circuit device includes:
a first semiconductor chip; and
a second semiconductor chip, the first and second semiconductor chips being stacked one on top of the other,
a back surface of the first semiconductor chip and a principal surface of the second semiconductor chip face each other,
the first semiconductor chip includes:
a plurality of transistors,
a plurality of first power supply lines extending in a first direction, arranged at a first pitch in a second direction perpendicular to the first direction in plan view, for supplying a first power supply voltage to the plurality of transistors, and
a plurality of first vias formed from the back surface of the first semiconductor chip to reach the first power supply lines,
the second semiconductor chip includes:
a plurality of second power supply lines formed in a first wiring layer that is a wiring layer closest to the principal surface of the second semiconductor chip, extending in the first direction and arranged at the first pitch in the second direction in plan view,
the first power supply lines are connected with the second power supply lines through the plurality of first vias, and
the second power supply lines in the second semiconductor chip of the semiconductor integrated circuit device are electrically connected to the external terminal.