US 12,068,287 B2
Stacked semiconductor structure and method
Szu-Ying Chen, Toufen Township (TW); Meng-Hsun Wan, Taipei (TW); and Dun-Nian Yaung, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 17, 2023, as Appl. No. 18/170,790.
Application 15/018,490 is a division of application No. 14/250,024, filed on Apr. 10, 2014, granted, now 9,257,414, issued on Feb. 9, 2016.
Application 18/170,790 is a continuation of application No. 17/223,292, filed on Apr. 6, 2021, granted, now 11,587,910.
Application 17/223,292 is a continuation of application No. 16/679,598, filed on Nov. 11, 2019, granted, now 11,037,909, issued on Jun. 15, 2021.
Application 16/679,598 is a continuation of application No. 16/221,734, filed on Dec. 17, 2018, granted, now 10,510,730, issued on Dec. 17, 2019.
Application 16/221,734 is a continuation of application No. 15/657,630, filed on Jul. 24, 2017, granted, now 10,157,889, issued on Dec. 18, 2018.
Application 15/657,630 is a continuation of application No. 15/018,490, filed on Feb. 8, 2016, granted, now 9,716,078, issued on Jul. 25, 2017.
Prior Publication US 2023/0207530 A1, Jun. 29, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/50 (2013.01); H01L 2224/03019 (2013.01); H01L 2224/033 (2013.01); H01L 2224/03452 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/03464 (2013.01); H01L 2224/03616 (2013.01); H01L 2224/0384 (2013.01); H01L 2224/03848 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/05546 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/08058 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80357 (2013.01); H01L 2224/8083 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/80948 (2013.01); H01L 2224/80986 (2013.01); H01L 2224/9202 (2013.01); H01L 2225/06548 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01074 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, the method comprising:
bonding a first chip to a second chip, the first chip comprising:
a first substrate;
a first insulating layer;
a first interconnect structure interposed between the first insulating layer and the first substrate;
a first aluminum connection pad embedded in the first insulating layer; and
a first copper bonding pad embedded in the first insulating layer, wherein the first aluminum connection pad directly contacts the first copper bonding pad; and
the second chip comprising:
a second substrate;
a second interconnect structure;
a second insulating layer, the second interconnect structure being interposed between the second insulating layer and the second substrate; and
a second copper bonding pad embedded in the second insulating layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first copper bonding pad and the second copper bonding pad, wherein the first copper bonding pad and the second copper bonding pad comprise a single homogenous copper layer, wherein a width of the first copper bonding pad is different than a width of the second copper bonding pad.