US 12,068,285 B2
Stacked die structure and method of fabricating the same
Jie Chen, New Taipei (TW); Hsien-Wei Chen, Hsinchu (TW); and Ming-Fa Chen, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 21, 2022, as Appl. No. 17/676,233.
Application 17/676,233 is a division of application No. 16/876,108, filed on May 17, 2020, granted, now 11,257,791.
Claims priority of provisional application 62/892,556, filed on Aug. 28, 2019.
Prior Publication US 2022/0173077 A1, Jun. 2, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 24/13 (2013.01); H01L 25/50 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A stacked die structure, comprising:
a base die comprising:
a base semiconductor substrate;
a base interconnection layer disposed on the base semiconductor substrate; and
a base bonding layer disposed on and electrically connected to the base interconnection layer;
a top die stacked on the base die and electrically connected to the base die, wherein the top die comprises:
a top bonding layer hybrid bonded to the base bonding layer of the base die;
a top semiconductor substrate disposed on the top bonding layer;
a top interconnection layer disposed on the top semiconductor substrate, wherein the top interconnection layer comprises a dielectric layer, a plurality of conductive layers embedded in the dielectric layer, and a plurality of conductive vias joining the plurality of conductive layers; and
top conductive pads and top grounding vias embedded in the dielectric layer and disposed on the plurality of conductive layers; and
a plurality of conductive terminals electrically connected to the top die.