US 12,068,284 B2
Vertical interconnect structures with integrated circuits
Tzu-Hsien Yang, Hsinchu (TW); Hiroki Noguchi, Hsinchu (TW); Mahmut Sinangil, Campbell, CA (US); and Yih Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 29, 2021, as Appl. No. 17/537,026.
Claims priority of provisional application 63/164,019, filed on Mar. 22, 2021.
Prior Publication US 2022/0302088 A1, Sep. 22, 2022
Int. Cl. H01L 25/18 (2023.01); H01L 25/065 (2023.01); H01L 21/768 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 25/18 (2013.01); H01L 21/76898 (2013.01); H01L 2225/06544 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A 3D integrated circuit structure, comprising:
a first die layer; and
a second die layer disposed over the first die layer, the second die layer comprising:
a device;
a vertical interconnect structure (VIS) cell disposed adjacent to the device; and
a non-sensitive circuit disposed in the VIS cell,
wherein the device is a first device, the first die layer includes a second device, and the second device is a different type of device from a type of device of the first device to produce a heterogeneous 3D integrated circuit structure.