US 12,068,266 B2
Hybrid coating for integrated circuit device
Jarrod N. Vaillancourt, South Hampton, NH (US); and William J. Davis, Hollis, NH (US)
Assigned to Raytheon Technologies Corporation, Tewksbury, MA (US)
Filed by Raytheon Company, Waltham, MA (US)
Filed on Dec. 23, 2021, as Appl. No. 17/561,113.
Prior Publication US 2023/0207497 A1, Jun. 29, 2023
Int. Cl. H01L 23/66 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/66 (2013.01) [H01L 23/3114 (2013.01); H01L 23/49861 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a wafer; and
an interconnect layer at least partially covering the wafer, the interconnect layer comprising:
a low radio frequency (RF) loss primary coating that forms a main portion of the interconnect layer;
a trench formed in and extending through a full thickness of the primary coating to expose a feature that is positioned on the wafer;
a high aspect ratio patternable secondary coating within the trench; and
a via formed in the secondary coating, wherein an aspect ratio of the via is greater than an aspect ratio of the trench.