US 12,068,256 B2
Method of manufacturing a three dimensional integrated semiconductor architecture having alignment marks provided in a carrier substrate
Seok Won Cho, Watervliet, NY (US); Ki-Il Kim, Clifton Park, NY (US); and Kang Ill Seo, Springfield, VA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 18, 2023, as Appl. No. 18/319,765.
Application 18/319,765 is a continuation of application No. 17/157,374, filed on Jan. 25, 2021, granted, now 11,694,968.
Claims priority of provisional application 63/113,626, filed on Nov. 13, 2020.
Prior Publication US 2023/0290734 A1, Sep. 14, 2023
Int. Cl. H01L 23/544 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01)
CPC H01L 23/544 (2013.01) [H01L 23/481 (2013.01); H01L 24/83 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/8313 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor architecture, the method including:
providing a first wafer comprising a carrier substrate;
providing a stopper layer on the carrier substrate;
providing a sacrificial layer on the stopper layer;
providing alignment marks in the carrier substrate from a first surface of the carrier substrate to a first surface of the stopper layer;
providing a first semiconductor device on the first surface of the carrier substrate based on locations of the alignment marks provided on the first surface of the carrier substrate;
removing the sacrificial layer;
removing the stopper layer; and
providing a second semiconductor device on a second surface of the carrier substrate based on locations of the alignment marks provided on the second surface of the carrier substrate,
wherein providing the second semiconductor device further comprises providing a through silicon via (TSV) based on the locations of the alignment marks such that the through silicon via is aligned with a buried power rail (BPR) included in the first semiconductor device.