US 12,068,255 B2
Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
M. Jared Barclay, Middleton, ID (US); John D. Hopkins, Meridian, ID (US); Richard J. Hill, Boise, ID (US); Indra V. Chary, Boise, ID (US); and Kar Wui Thong, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 11, 2021, as Appl. No. 17/399,283.
Prior Publication US 2023/0052468 A1, Feb. 16, 2023
Int. Cl. H10B 43/27 (2023.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H10B 41/27 (2023.01)
CPC H01L 23/535 (2013.01) [H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 36 Claims
OG exemplary drawing
 
1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers above the conductor tier, the stack comprising laterally-spaced memory-block regions, the memory-block regions comprising part of a memory-plane region, the lower portion comprising a lowest of the first tiers that comprises sacrificial material;
forming a wall in the lowest first tier aside the sacrificial material, the wall being of different composition from that of the sacrificial material and being horizontally-elongated, the wall being one of (a) or (b), where:
(a): in the memory-plane region longitudinally-along one of the memory-block regions, the one memory-block region being immediately-adjacent a through-array-via (TAV) region that is in the memory-plane region, the wall being along an edge of the one memory-block region that is closest to the TAV region that is in the memory-plane region; and
(b): in a region that is edge-of-plane relative to the memory-plane region, the edge-of-plane region comprising a TAV region, the wall being horizontally-elongated relative to an edge of the TAV region that is in the edge-of-plane region;
after forming the wall, forming the vertically-alternating different-composition first tiers and second tiers of an upper portion of the stack above the lower portion, and forming channel-material strings that extend through the first tiers and the second tiers in the upper portion to the lower portion;
forming horizontally-elongated trenches through the upper portion and that are individually between immediately-laterally-adjacent of the memory-block regions; and
through the horizontally-elongated trenches, isotropically etching the sacrificial material selectively relative to the wall and replacing the sacrificial material with conducting material that directly electrically couples together channel material of the channel-material strings and the conductor material of the conductor tier.