CPC H01L 23/528 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76877 (2013.01)] | 9 Claims |
1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a memory cell array region and a peripheral circuit region;
forming a first insulating dielectric layer in the memory cell array region and forming a second insulating dielectric layer in the peripheral circuit region, wherein bit line structures spaced apart from each other are formed in the first insulating dielectric layer, conductive structures spaced apart from each other are formed in the second insulating dielectric layer, and each of the bit line structures comprises a bit line conductive structure and an isolation structure covering a top and a side wall of the bit line conductive structure;
etching the isolation structure to form a first gap in the memory cell array region and etching the second insulating dielectric layer between the conductive structures in the peripheral circuit region to form a second gap in the peripheral circuit region, wherein the first gap at least partly exposes the bit line conductive structure, and the second gap exposes the substrate between the conductive structures in the peripheral circuit region; and
forming a third insulating dielectric layer on a side wall of the first gap and a side wall of the second gap, wherein a thickness of the third insulating dielectric layer on the side wall of the first gap and a thickness of the isolation structure on a side wall of each of the bit line structures are the same or different from each other.
|