| CPC H01L 23/5226 (2013.01) [H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76897 (2013.01); H01L 29/6656 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
|
1. A semiconductor device, comprising:
a substrate;
a gate pattern on the substrate, the gate pattern including a gate dielectric layer, a gate electrode, and a gate capping pattern that are sequentially stacked;
a gate spacer that covers a sidewall of the gate pattern;
a source/drain pattern in the substrate at a side of the gate pattern;
a metal contact pad on the source/drain pattern, the metal contact pad having a top surface lower than a top surface of the gate electrode;
a source/drain contact on the metal contact pad; and
a buried dielectric pattern between the gate spacer and the source/drain contact, the buried dielectric pattern surrounding the source/drain contact,
wherein:
the gate spacer includes:
a first segment between the gate electrode and the source/drain pattern, the first segment having a first width;
a second segment that extends from the first segment and is between the gate electrode and the source/drain contact, the second segment having the first width; and
a third segment on the second segment, the third segment having a second width that is less than the first width,
the buried dielectric pattern is between the third segment and the source/drain contact, and
the buried dielectric pattern is absent between the first segment and the metal contact pad and is absent between the second segment and the source/drain contact,
wherein the semiconductor device further comprises:
a first dielectric spacer between the second segment and the source/drain contact, the first dielectric spacer being spaced apart from the third segment, and
a second dielectric spacer between the first dielectric spacer and the source/drain contact, and
wherein the first dielectric spacer and the second dielectric spacer are in contact with an upper surface of the metal contact pad.
|