US 12,068,237 B2
Dual circuit digital isolator
Sundar Chetlur, Frisco, TX (US); Maxim Klebanov, Palm Coast, FL (US); Cory Voisine, Manchester, NH (US); Kenneth Snowdon, Stratham, NH (US); and Hsuan-Jung Wu, Taoyuan (TW)
Assigned to Allegro MicroSystems, LLC, Manchester, NH (US)
Filed by Allegro MicroSystems, LLC, Manchester, NH (US)
Filed on Oct. 31, 2022, as Appl. No. 18/051,151.
Application 18/051,151 is a division of application No. 17/067,178, filed on Oct. 9, 2020, granted, now 11,515,246.
Prior Publication US 2023/0084169 A1, Mar. 16, 2023
Int. Cl. H01L 23/52 (2006.01); H01L 21/8234 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/5222 (2013.01) [H01L 21/823493 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising;
a substrate;
an isolator that is formed over the substrate, the isolator including a silicon shield layer that is formed between a first buried oxide (BOX) layer and a second BOX layer;
a silicon layer having an oxide trench structure formed therein, the oxide trench structure being arranged to define a first silicon island and a second silicon island;
a first electronic circuit that is formed over the first silicon island; and
a second electronic circuit that is formed over the second silicon island, the second electronic circuit being electrically coupled to the first electronic circuit.