US 12,068,233 B2
Adapter board and method for forming same, packaging method, and package structure
Cai Qiaoming, Beijing (CN); Yang Lie Yong, Beijing (CN); Chen Wei, Beijing (CN); and Lu Xiao Yu, Beijing (CN)
Assigned to Semiconductor Manufacturing North China (Beijing) Corporation, Beijing (CN)
Filed by Semiconductor Manufacturing North China (Beijing) Corporation, Beijing (CN)
Filed on Mar. 21, 2023, as Appl. No. 18/124,069.
Application 18/124,069 is a division of application No. 17/155,450, filed on Jan. 22, 2021, granted, now 11,637,059.
Claims priority of application No. 202010571641.8 (CN), filed on Jun. 22, 2020.
Prior Publication US 2023/0223329 A1, Jul. 13, 2023
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/64 (2006.01); H01L 49/02 (2006.01)
CPC H01L 23/49838 (2013.01) [H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/49822 (2013.01); H01L 23/642 (2013.01); H01L 24/81 (2013.01); H01L 28/91 (2013.01); H01L 28/92 (2013.01); H01L 2224/8136 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method for forming an adapter board, comprising:
providing a base comprising:
an interconnect region used for forming a via interconnect structure thereon and a capacitor region used for forming a capacitor thereon, and
a front surface and a rear surface that are opposite each other;
etching the front surface of the base to form a first trench in the base of the interconnect region and to form a second trench in the base of the capacitor region;
forming a capacitor in the second trench, the capacitor comprising a first electrode located on side walls and a bottom of the second trench, a capacitor dielectric layer located on the first electrode, and a second electrode located on the capacitor dielectric layer, the second electrode filling the second trench;
etching a partial thickness of the base under the first trench after the capacitor is formed, to form a groove in the base, the groove and the first trench forming a conductive via;
forming a via interconnect structure in the conductive via; and
thinning the rear surface of the base, to expose the via interconnect structure from the rear surface of the base.