US 12,068,221 B2
Plating for thermal management
Nazila Dadvand, Richardson, TX (US); Christopher Daniel Manack, Flower Mound, TX (US); and Salvatore Frank Pavone, Murphy, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Aug. 4, 2020, as Appl. No. 16/985,103.
Application 16/985,103 is a continuation of application No. 16/193,089, filed on Nov. 16, 2018, granted, now 10,734,304.
Prior Publication US 2020/0365483 A1, Nov. 19, 2020
Int. Cl. H01L 23/373 (2006.01); C23C 14/16 (2006.01); C23C 18/38 (2006.01); C25D 3/38 (2006.01); C25D 3/46 (2006.01); H01L 21/285 (2006.01); H01L 21/288 (2006.01); H01L 21/768 (2006.01); H01L 21/78 (2006.01)
CPC H01L 23/3736 (2013.01) [C23C 14/165 (2013.01); C23C 18/38 (2013.01); C25D 3/38 (2013.01); C25D 3/46 (2013.01); H01L 21/2855 (2013.01); H01L 21/288 (2013.01); H01L 21/76873 (2013.01); H01L 21/78 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A process for making a semiconductor device, comprising:
forming a first diffusion barrier layer on an active side of a semiconductor wafer;
forming a second diffusion barrier layer on a backside of the semiconductor wafer;
forming a first seed copper layer on the first diffusion barrier layer;
forming a second seed copper layer on the second diffusion barrier layer;
forming a first copper layer on the first seed copper layer;
forming a second copper layer on the second seed copper layer; and
immersion plating a silver layer on the second copper layer.