US 12,068,197 B2
Methods for forming contact plugs with reduced corrosion
Yu-Sheng Wang, Tainan (TW); Chi-Cheng Hung, Tainan (TW); Chen-Yuan Kao, Zhudong Township (TW); Yi-Wei Chiu, Kaohsiung (TW); Liang-Yueh Ou Yang, New Taipei (TW); and Yueh-Ching Pai, Taichung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 19, 2021, as Appl. No. 17/234,136.
Application 17/234,136 is a continuation of application No. 16/678,410, filed on Nov. 8, 2019, granted, now 10,985,061.
Application 16/678,410 is a continuation of application No. 16/213,326, filed on Dec. 7, 2018, granted, now 10,483,165, issued on Nov. 19, 2019.
Application 16/213,326 is a continuation of application No. 15/492,113, filed on Apr. 20, 2017, granted, now 10,186,456, issued on Jan. 22, 2019.
Prior Publication US 2021/0257254 A1, Aug. 19, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 21/288 (2006.01); H01L 23/485 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/285 (2006.01)
CPC H01L 21/76895 (2013.01) [H01L 21/2885 (2013.01); H01L 21/76829 (2013.01); H01L 21/76831 (2013.01); H01L 21/7684 (2013.01); H01L 21/76849 (2013.01); H01L 21/76874 (2013.01); H01L 21/76877 (2013.01); H01L 21/76879 (2013.01); H01L 21/76883 (2013.01); H01L 29/41775 (2013.01); H01L 29/66477 (2013.01); H01L 29/665 (2013.01); H01L 29/66553 (2013.01); H01L 29/78 (2013.01); H01L 29/7833 (2013.01); H01L 21/28518 (2013.01); H01L 21/76843 (2013.01); H01L 21/76855 (2013.01); H01L 21/76873 (2013.01); H01L 23/485 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a semiconductor region;
a gate stack over the semiconductor region;
a source/drain region in the semiconductor region;
a contact plug over and electrically coupling to the gate stack or the source/drain region, the contact plug comprising:
a metal feature; and
a first layer comprising sidewall portions on opposite sides of the metal feature, and a bottom portion overlapped by the metal feature; and
a conductive layer comprising:
a middle portion overlapping and contacting the metal feature; and
an end portion on a side of the middle portion, wherein the end portion is thicker than the middle portion, wherein the end portion that is thicker than the middle portion also overlaps an inner portion of one of the sidewall portions of the first layer, and wherein a curved interface is formed between the end portion and the metal feature.