US 12,068,172 B2
Sacrificial pads to prevent galvanic corrosion of FLI bumps in EMIB packages
Tarek A. Ibrahim, Mesa, AZ (US); Rahul N. Manepalli, Chandler, AZ (US); Wei-Lun K. Jen, Chandler, AZ (US); Steve S. Cho, Chandler, AZ (US); Jason M. Gamba, Gilbert, AZ (US); and Javier Soto Gonzalez, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 30, 2019, as Appl. No. 16/525,985.
Prior Publication US 2021/0035818 A1, Feb. 4, 2021
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/538 (2006.01)
CPC H01L 21/4846 (2013.01) [H01L 21/481 (2013.01); H01L 23/49838 (2013.01); H01L 23/5386 (2013.01); H01L 23/5385 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19105 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An electronic package, comprising:
a package substrate;
an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, and each of the FLI bumps on a corresponding pad;
a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad; and
a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad, wherein the second pad does not comprise the surface finish, and wherein the second pad, the first pad, and the corresponding pads are all at a same level.