US 12,068,167 B2
Self-aligned double patterning
Kuan-Wei Huang, Taoyuan (TW); Yu-Yu Chen, Hsinchu (TW); and Jyu-Horng Shieh, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 12, 2023, as Appl. No. 18/316,620.
Application 18/316,620 is a continuation of application No. 17/883,930, filed on Aug. 9, 2022, granted, now 11,784,056.
Application 17/883,930 is a continuation of application No. 17/018,705, filed on Sep. 11, 2020, granted, now 11,676,821.
Claims priority of provisional application 62/927,336, filed on Oct. 29, 2019.
Prior Publication US 2023/0282488 A1, Sep. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01)
CPC H01L 21/3085 (2013.01) [H01L 21/3088 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76898 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
patterning a first patterning layer over a target layer to form a first pattern and a second pattern;
depositing a spacer structure over the first pattern and the second pattern;
masking a first portion of the spacer structure overlying the first pattern, a second portion of the spacer structure exposed from the mask;
etching the second portion of the spacer structure to at least thin the second portion of the spacer structure;
unmasking the first portion of the spacer structure;
forming a spacer mask, wherein forming the spacer mask comprises anisotropically etching the first portion of the spacer structure;
removing the first pattern, leaving behind the spacer mask; and
etching the target layer based on the spacer mask.