US 12,068,157 B2
Method of manufacturing semiconductor device
Hyun Seung Ha, Yongin-si (KR); Jang Hoon Kim, Seoul (KR); Tae-Kyu Kim, Hwaseong-si (KR); Young Kuk Byun, Suwon-si (KR); and Jong Hyun Jung, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 26, 2021, as Appl. No. 17/385,069.
Claims priority of application No. 10-2020-0166728 (KR), filed on Dec. 2, 2020.
Prior Publication US 2022/0172944 A1, Jun. 2, 2022
Int. Cl. H01L 21/027 (2006.01); G03F 7/00 (2006.01); G03F 7/20 (2006.01); H01L 21/66 (2006.01)
CPC H01L 21/0274 (2013.01) [G03F 7/70633 (2013.01); H01L 22/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, comprising:
forming a first lower overlay key including first and second patterns in a lower layer;
forming a first upper overlay key including third and fourth patterns in an upper layer vertically disposed on the lower layer;
irradiating a first measurement light to a first region of interest (ROI) over first portions of the first and second patterns to detect a first overlay error; and
irradiating a second measurement light to a second ROI over second portions of the first and second patterns, the second ROI being different from the first ROI, to detect a second overlay error, wherein the second measurement light has a different central frequency than the first measurement light.