US 12,068,117 B2
Multilayer ceramic capacitor
Keita Kitahara, Nagaokakyo (JP); Yuta Saito, Nagaokakyo (JP); Noriyuki Ookawa, Nagaokakyo (JP); Riyousuke Akazawa, Nagaokakyo (JP); Takefumi Takahashi, Nagaokakyo (JP); Masahiro Wakashima, Nagaokakyo (JP); Yuta Kurosu, Nagaokakyo (JP); and Akito Mori, Nagaokakyo (JP)
Assigned to MURATA MANUFACTURING CO., LTD., Kyoto (JP)
Filed by Murata Manufacturing Co., Ltd., Nagaokakyo (JP)
Filed on Oct. 2, 2023, as Appl. No. 18/375,681.
Application 18/375,681 is a continuation of application No. 17/487,353, filed on Sep. 28, 2021, granted, now 11,810,725.
Claims priority of application No. 2020-166436 (JP), filed on Sep. 30, 2020.
Prior Publication US 2024/0029958 A1, Jan. 25, 2024
Int. Cl. H01G 4/30 (2006.01); H01G 4/008 (2006.01); H01G 4/012 (2006.01); H01G 4/12 (2006.01)
CPC H01G 4/30 (2013.01) [H01G 4/008 (2013.01); H01G 4/012 (2013.01); H01G 4/1218 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A multilayer ceramic capacitor comprising:
a multilayer body including:
a laminate chip including an inner layer portion including dielectric layers and internal electrode layers laminated therein, and outer layer portions respectively provided on both side surfaces of the inner layer portion in a lamination direction;
side gap portions respectively provided on both side surfaces of the laminate chip in a width direction intersecting the lamination direction; and
external electrodes respectively provided on both side surfaces of the multilayer body in a length direction intersecting the lamination direction and the width direction, and each connected to the internal electrode layers; wherein
nickel and magnesium are segregated in a boundary region between the side gap portions and the outer layer portions.