US 12,068,057 B2
Processing system, related integrated circuit, device and method
Asif Rashid Zargar, Greater Noida (IN); Nicolas Bernard Grossier, Oreno di Vimercate (IT); Charul Jain, Delhi (IN); and Roberto Colombo, Munich (DE)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (MB) (IT); STMicroelectronics Aplication GmbH, Aschheim-Dornach (DE); and STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT); STMicroelectronics International N.V., Geneva (CH); and STMicroelectronics Application GMBH, Aschheim-Dornach (DE)
Filed on Nov. 18, 2022, as Appl. No. 18/056,803.
Claims priority of application No. 102021000030332 (IT), filed on Nov. 30, 2021.
Prior Publication US 2023/0170006 A1, Jun. 1, 2023
Int. Cl. G11C 7/24 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/24 (2013.01) [G11C 7/1039 (2013.01); G11C 7/1069 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A processing system comprising:
a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop;
a non-volatile memory configured to store data bits for the plurality of storage elements;
a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements; and
a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements,
wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop,
wherein the first storage element comprises a combinational logic circuit configured to:
compare the logic level stored to the latch or the flip-flop of the first storage element with a logic level stored to the further latch or the further flip-flop of the first storage element,
de-assert a first tamper signal associated with the first storage element when the logic levels are different, and
assert the first tamper signal when the logic levels are the same, and
wherein the hardware circuit is further configured to change operation as a function of the first tamper signal.