US 12,068,056 B2
Semiconductor chip and semiconductor system
Young Sub Yuk, Icheon-si (KR); and Jae Woo Song, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Oct. 31, 2022, as Appl. No. 17/977,249.
Claims priority of application No. 10-2022-0079807 (KR), filed on Jun. 29, 2022.
Prior Publication US 2024/0005970 A1, Jan. 4, 2024
Int. Cl. G11C 7/20 (2006.01); G01R 19/175 (2006.01); G11C 7/22 (2006.01); G11C 11/4072 (2006.01)
CPC G11C 7/20 (2013.01) [G01R 19/175 (2013.01); G11C 7/22 (2013.01); G11C 11/4072 (2013.01)] 32 Claims
OG exemplary drawing
 
1. A semiconductor chip comprising:
a detection circuit configured to generate a discharge signal that is enabled when a voltage level of an external voltage is greater than a first set level and configured to generate a voltage control signal that is enabled when, in a test mode, an output voltage is generated to have a voltage level of a ground voltage;
a charge discharge circuit configured to, when the discharge signal is enabled, discharge charges of an output node that is included in a driving circuit; and
the driving circuit configured to generate the output voltage by supplying charges from the external voltage to the output node in response to a driving signal,
wherein the voltage level of the output voltage increases to a second set level, and
wherein a voltage level of the driving signal is decreased during an interval in which the voltage control signal is enabled.