CPC G11C 7/20 (2013.01) [G01R 19/175 (2013.01); G11C 7/22 (2013.01); G11C 11/4072 (2013.01)] | 32 Claims |
1. A semiconductor chip comprising:
a detection circuit configured to generate a discharge signal that is enabled when a voltage level of an external voltage is greater than a first set level and configured to generate a voltage control signal that is enabled when, in a test mode, an output voltage is generated to have a voltage level of a ground voltage;
a charge discharge circuit configured to, when the discharge signal is enabled, discharge charges of an output node that is included in a driving circuit; and
the driving circuit configured to generate the output voltage by supplying charges from the external voltage to the output node in response to a driving signal,
wherein the voltage level of the output voltage increases to a second set level, and
wherein a voltage level of the driving signal is decreased during an interval in which the voltage control signal is enabled.
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