US 12,068,051 B2
Built-in high-frequency test circuitry without duty distortion
Hoon Choi, Santa Clara, CA (US); Anil Pai, San Jose, CA (US); and Venkatesh Prasad Ramachandra, San Jose, CA (US)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on May 20, 2022, as Appl. No. 17/749,813.
Prior Publication US 2023/0377677 A1, Nov. 23, 2023
Int. Cl. G11C 29/54 (2006.01); G06F 1/08 (2006.01); G11C 16/04 (2006.01)
CPC G11C 29/54 (2013.01) [G06F 1/08 (2013.01); G11C 16/0483 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method of performing wafer-level testing of NAND flash memory, the method comprising:
receiving a strobe clock signal at an input buffer of the NAND flash memory;
performing a first sweep of the strobe clock signal, wherein performing the first sweep comprises using a rising edge of the strobe clock signal to locate one of even or odd data in the input buffer;
performing a second sweep of an inverted strobe clock signal obtained by inverting the strobe clock signal, wherein performing the second sweep comprises using a rising edge of the inverted strobe clock signal to locate the other of the even or odd data in the input buffer; and
measuring a valid data window of data in the input buffer based on the first sweep and the second sweep.