US 12,068,048 B2
Processing system error management, related integrated circuit, apparatus and method
Vivek Mohan Sharma, New Delhi (IN); and Roberto Colombo, Munich (DE)
Assigned to TMicroelectronics Application GMBH, Aschheim-Dornach (DE); and STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics Application GMBH, Aschheim-Dornach (DE); and STMicroelectronics International N.V., Geneva (CH)
Filed on Jul. 28, 2022, as Appl. No. 17/815,807.
Claims priority of application No. 102021000022565 (IT), filed on Aug. 31, 2021.
Prior Publication US 2023/0065623 A1, Mar. 2, 2023
Int. Cl. G11C 29/24 (2006.01); G11C 29/36 (2006.01); G11C 29/42 (2006.01); G11C 29/48 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 29/36 (2013.01); G11C 29/48 (2013.01); G11C 2029/3602 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processing system comprising:
a circuit configured to provide a given number N of data bits and a given number K of Error Correction Code (ECC) bits;
an error detection circuit configured to:
receive the data bits and the ECC bits;
calculate further ECC bits as a function of the data bits according to a given ECC scheme;
generate a syndrome by comparing the calculated ECC bits with the received ECC bits, wherein the syndrome has K bits;
compare the syndrome with a plurality of N+K single bit-flip reference syndromes, wherein each single bit-flip reference syndrome is associated with a respective single bit-flip error; and
in response to determining that the syndrome corresponds to a single bit-flip reference syndrome:
assert a first error signal; and
assert one bit of a bit-flip signature corresponding to the single bit-flip error indicated by the respective single bit-flip reference syndrome, wherein the bit-flip signature has a given number N+K bits and indicates a position of one or more incorrect bits in the data bits and ECC bits; and
a test circuit configured to:
provide, during a test-mode, a sequence of patterns to the error detection circuit, each pattern comprising data bits and ECC bits, and monitor the respective first error signal and bit-flip signature;
obtain a first pattern, the first pattern corresponding to a given sequence of data bits and ECC bits calculated as a function of the given data bits according to the given ECC scheme;
provide the first pattern to the error detection circuit and verify whether the first error signal is de-asserted and all bits of the bit-flip signature are de-asserted;
obtain a sequence of N+K further bit-flip signatures, each further bit-flip signature having asserted a single bit;
obtain for each further bit-flip signature a respective second pattern, wherein each second pattern corresponds to a pattern having a single bit flipped with respect to a reference pattern at positions of the single asserted bit of the respective further bit-flip signature, wherein the reference pattern corresponds to a given sequence of data bits and ECC bits calculate as a function of the respective data bits according to the given ECC scheme, wherein each second pattern corresponds to a pattern with a correctable single bit error;
provide each of the second patterns to the error detection circuit and verify whether the first error signal is asserted and the bit-flip signature corresponds to the respective further bit-flip signature; and
assert one or more error signals in response to determining that:
for the first pattern, the first error signal is asserted and/or at least one bit of the bit-flip signature is asserted; and/or
for each of the second patterns, the first error signal is de-asserted and/or the bit-flip signature does not correspond to the respective further bit-flip signature.