US 12,068,046 B2
Memory device and operating method thereof
Jang Seob Kim, Gyeonggi-do (KR); and Sang Ho Yun, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on May 31, 2022, as Appl. No. 17/828,262.
Claims priority of application No. 10-2021-0173978 (KR), filed on Dec. 7, 2021.
Prior Publication US 2023/0178159 A1, Jun. 8, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A storage device comprising:
a memory device including a plurality of memory cells, and configured to perform a read operation of reading data stored in selected memory cells among the plurality of memory cells; and
a memory controller configured to receive a read request from a host and control the memory device to perform the read operation corresponding to the read request,
wherein the memory controller includes a read voltage inferrer configured to:
receive, when the read operation is completed, read information on the read operation from the memory device,
perform a read quality evaluation operation of evaluating the read operation, based on the read information, and
perform a read voltage inference operation of inferring a secondary read level corresponding to the read information according to a result of the performing the read quality evaluation operation, and
wherein the read voltage inferrer infers a peak voltage level corresponding to each program state based on read voltage levels used in the read operation, and the secondary read level by using the inferred peak voltage level.