US 12,068,045 B2
Semiconductor memory device and operating method thereof
Hyung Jin Choi, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Dec. 30, 2021, as Appl. No. 17/566,306.
Claims priority of application No. 10-2021-0108067 (KR), filed on Aug. 17, 2021.
Prior Publication US 2023/0058168 A1, Feb. 23, 2023
Int. Cl. G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/3445 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory cell array circuit including a plurality of memory cells that are coupled to a plurality of word lines; and
a driving force adjustment circuit configured to adjust, based on a location of a verify target memory cell, driving forces of a plurality of respective verify pass voltages that are applied to unselected word lines among the plurality of word lines,
wherein each of the verify pass voltages reaches a corresponding target voltage level more quickly as a corresponding driving force increases.