CPC G11C 16/34 (2013.01) [G06F 11/1068 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 29/52 (2013.01); G11C 16/0483 (2013.01)] | 12 Claims |
1. A memory system comprising:
a semiconductor memory including memory cells and a word line coupled to the memory cells, each of the memory cells being capable of storing four-bit data, and
a controller configured to:
read a first data item from the memory cells through application of a first voltage to the word line;
repeat a first operation to read first bit data in each of the memory cells, the first operation including applying a second voltage to the word line, the first operation including applying a third voltage to the word line after applying the second voltage, the third voltage having a magnitude different from that of the second voltage, the second voltage being changed within a first range every time the first operation is repeated, the third voltage being changed within a second range every time the first operation is repeated;
read a plurality of second data items by the repeating of the first operation; and
mask part of each of the second data items using the first data item.
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