US 12,068,043 B2
Semiconductor memory device
Masato Dome, Yokohama Kanagawa (JP); Kensuke Yamamoto, Yokohama Kanagawa (JP); Masaru Koyanagi, Tokyo (JP); Ryo Fukuda, Yokohama Kanagawa (JP); Junya Matsuno, Yokohama Kanagawa (JP); and Kenro Kubota, Fujisawa Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Oct. 3, 2022, as Appl. No. 17/959,098.
Application 17/959,098 is a continuation of application No. 17/202,590, filed on Mar. 16, 2021, granted, now 11,495,307.
Claims priority of application No. 2020-157800 (JP), filed on Sep. 18, 2020.
Prior Publication US 2023/0028971 A1, Jan. 26, 2023
Int. Cl. G11C 16/30 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/30 (2013.01) [G11C 16/0483 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory cell array including a memory cell configured to store data;
a sense amplifier connected to the memory cell;
a data register connected to the sense amplifier;
an input/output circuit connected to the data register; and
a pad group connected to the input/output circuit,
wherein
the pad group includes
a first power supply pad to which a first voltage is supplied;
a second power supply pad to which a second voltage different from the first voltage is supplied; and
a first input/output pad, and
the input/output circuit includes
a first circuit unit supplied with the first voltage and the second voltage, and configured to receive a first signal from the data register and output a second signal predicated on the first signal;
a second circuit unit supplied with the first voltage and the second voltage, and configured to receive the second signal and output a third signal predicated on the second signal;
a first driver circuit configured to receive a fourth signal predicated on the third signal and output a fifth signal predicated on the fourth signal toward the first input/output pad;
a first interconnect connected between the first circuit unit and the first power supply pad; and
a second interconnect connected between the second circuit unit and the first power supply pad, the second interconnect being physically separated from the first interconnect.