US 12,068,039 B2
Memory device and method of operating the same
Jae Il Tak, Icheon-si Gyeonggi-do (KR)
Assigned to SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Aug. 22, 2022, as Appl. No. 17/892,600.
Claims priority of application No. 10-2022-0036321 (KR), filed on Mar. 23, 2022.
Prior Publication US 2023/0307063 A1, Sep. 28, 2023
Int. Cl. G11C 11/56 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 11/5642 (2013.01); G11C 11/5671 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory block including a plurality of memory cells that are coupled to a plurality of word lines;
a peripheral circuit configured to perform a read operation by applying a read voltage to a selected word line, among the plurality of word lines, and applying a first pass voltage to target word lines, wherein the target word lines are adjacent to the selected word line, among unselected word lines other than the selected word line; and
a control logic configured to:
decrease the read voltage based on a read voltage variation; and
decrease the first pass voltage based on a pass voltage variation when the read voltage decreases,
wherein the pass voltage variation is less than the read voltage variation.