US 12,068,037 B2
Managing sub-block erase operations in a memory sub-system
Kalyan Chakravarthy Kavalipurapu, Telangana (IN); Tomoko Ogura Iwasaki, San Jose, CA (US); Erwin E. Yu, San Jose, CA (US); Hong-Yan Chen, San Jose, CA (US); and Yunfei Xu, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 20, 2023, as Appl. No. 18/224,179.
Application 18/224,179 is a continuation of application No. 17/745,852, filed on May 16, 2022, granted, now 11,749,353.
Application 17/745,852 is a continuation of application No. 16/991,836, filed on Aug. 12, 2020, granted, now 11,335,412, issued on May 17, 2022.
Claims priority of provisional application 62/956,049, filed on Dec. 31, 2019.
Prior Publication US 2023/0360709 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/16 (2006.01); G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01)
CPC G11C 16/16 (2013.01) [G06F 3/0604 (2013.01); G06F 3/064 (2013.01); G06F 3/0652 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
connecting a first data block of the memory device to a second data block of the memory device to generate a combined data block comprising a first plurality of sub-blocks of the first data block and a second plurality of sub-blocks of the second data block, wherein the connecting comprises:
for each wordline of a first plurality of wordlines of the first data block, creating a wordline connection short between the respective wordline of the first data block and a corresponding wordline of a second plurality of wordlines of the second data block, wherein the first plurality of wordlines and the second plurality of wordlines comprise data wordlines; and
driving a first data wordline of the first data block and a second wordline of the second data block using a single string driver of the memory device.