US 12,068,034 B2
Two-pass corrective programming for memory cells that store multiple bits and power loss management for two-pass corrective programming
Kishore Kumar Muchherla, Fremont, CA (US); Huai-Yuan Tseng, San Ramon, CA (US); Giovanni Maria Paolucci, Milan (IT); Dave Scott Ebsen, Minnetonka, MN (US); James Fitzpatrick, Laguna Niguel, CA (US); Akira Goda, Tokyo (JP); Jeffrey S. McNeil, Nampa, ID (US); Umberto Siciliani, Rubano (IT); Daniel J. Hubbard, Boise, ID (US); Walter Di Francesco, Avezzano (IT); and Michele Incarnati, Avezzano (IT)
Assigned to MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 30, 2022, as Appl. No. 17/899,409.
Prior Publication US 2024/0071510 A1, Feb. 29, 2024
Int. Cl. G11C 16/10 (2006.01); G11C 16/08 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/08 (2013.01); G11C 16/3404 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a first set of data bits for programming to memory;
writing a first subset of data bits of the first set to a first wordline of the memory during a first pass of programming;
writing a second subset of data bits of the first set of data bits to a buffer, wherein the second subset of data bits is different than the first subset of data bits;
receiving a second set of data bits for programming, wherein the second set of data bits will be programmed to a second wordline; and
writing the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming in response to receiving the second set of data bits, the writing of the second subset of data bits including an increase in bit density of memory cells in the first wordline.