CPC G11C 16/08 (2013.01) [G11C 11/1657 (2013.01); H10B 12/053 (2023.02); H10B 41/30 (2023.02)] | 20 Claims |
1. An integrated chip comprising:
a substrate;
a first source/drain region in the substrate;
an erase gate, a control gate, and a word line overlying the substrate, wherein the control gate is between and borders the erase gate and the word line, and wherein the word line is between and borders the control gate and the first source/drain region;
a silicide layer atop the first source/drain region; and
a trench isolation structure underlying the word line;
wherein a bottom surface of the word line is recessed into a top surface of the trench isolation structure to an elevation, which is recessed relative to a top surface of the silicide layer.
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