US 12,068,031 B2
Semiconductor storage device
Jun Deguchi, Kawasaki Kanagawa (JP); Daisuke Miyashita, Kawasaki Kanagawa (JP); Atsushi Kawasumi, Fujisawa Kanagawa (JP); Hidehiro Shiga, Yokohama Kanagawa (JP); Shinji Miyano, Yokohama Kanagawa (JP); and Shinichi Sasaki, Ota Tokyo (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 1, 2022, as Appl. No. 17/901,239.
Claims priority of application No. 2022-046059 (JP), filed on Mar. 22, 2022.
Prior Publication US 2023/0307052 A1, Sep. 28, 2023
Int. Cl. G11C 16/08 (2006.01); G11C 8/08 (2006.01); G11C 8/10 (2006.01)
CPC G11C 16/08 (2013.01) [G11C 8/08 (2013.01); G11C 8/10 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A semiconductor storage device, comprising:
a memory cell array including a plurality of word line groups and a plurality of blocks corresponding to the plurality of word line groups, each of word line groups including a plurality of word lines and each of the blocks including a plurality of memory cells, the plurality of memory cells of each block being connected to the respective word lines of a corresponding one of the word line groups; and
a row decoder including a plurality of word line group decoders corresponding to the plurality of word line groups, respectively, wherein
each of the plurality of word line group decoders is configured to drive a word line independent from a word line driven in another of the word line groups, when all of the plurality of word line groups are activated in parallel.