US 12,068,026 B2
Low power and fast memory reset
Harsh Rawat, Haryana (IN); and Praveen Kumar Verma, Greater Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Jun. 29, 2022, as Appl. No. 17/852,677.
Claims priority of provisional application 63/221,090, filed on Jul. 13, 2021.
Prior Publication US 2023/0015002 A1, Jan. 19, 2023
Int. Cl. G11C 11/419 (2006.01); G11C 11/412 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 11/412 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of resetting a memory, comprising:
a) precharging bit lines of a memory array by applying a precharge voltage to the bit lines;
b) asserting a signal at a reset node to thereby remove the precharge voltage from the bit lines;
c) selecting write drivers associated with the bit lines associated with columns of the memory array that contain memory cells to be reset;
wherein the assertion of the signal at the reset node also results in assertion of inputs of the selected write drivers, thereby causing those selected write drivers to change a logic state of the bit lines associated with those write drivers;
d) asserting a word line associated with a row of the memory that contains memory cells to be reset, thereby writing desired logic states to all of the memory cells of the columns and row of the memory to be reset during a first clock cycle, and then deasserting that word line; and
e) without first reapplying the precharge voltage to the bit lines, asserting a word line associated with an other row of the memory that contains memory cells to be reset, thereby writing the desired logic states to all of the memory cells of the columns and the other row of the memory to be reset during a second clock cycle, and then deasserting that word line.