CPC G11C 11/418 (2013.01) [G11C 11/412 (2013.01)] | 19 Claims |
1. A device comprising:
memory having banks of bitcells with each bank having a bitcell array; and
header circuitry that powers-up a selected bank and powers-down unselected banks during a wake-up mode of operation,
wherein only the selected bank of the memory is powered-up with the header circuitry during the wake-up mode of operation, and
wherein the header circuitry includes power-gate transistors for each bank that are configured to be activated by one or more header control signals so as to selectively power-up the selected bank during the wake-up mode of operation.
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