US 12,068,025 B2
Power-up header circuitry for multi-bank memory
Rahul Mathur, Austin, TX (US); Edward Martin McCombs, Jr., Austin, TX (US); and Hsin-Yu Chen, Austin, TX (US)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Jul. 1, 2022, as Appl. No. 17/856,928.
Prior Publication US 2024/0005983 A1, Jan. 4, 2024
Int. Cl. G11C 11/00 (2006.01); G11C 11/412 (2006.01); G11C 11/418 (2006.01)
CPC G11C 11/418 (2013.01) [G11C 11/412 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A device comprising:
memory having banks of bitcells with each bank having a bitcell array; and
header circuitry that powers-up a selected bank and powers-down unselected banks during a wake-up mode of operation,
wherein only the selected bank of the memory is powered-up with the header circuitry during the wake-up mode of operation, and
wherein the header circuitry includes power-gate transistors for each bank that are configured to be activated by one or more header control signals so as to selectively power-up the selected bank during the wake-up mode of operation.