US 12,068,024 B2
Address dependent wordline timing in asynchronous static random access memory
Jay A. Chesavage, Palo Alto, CA (US); Robert Wiser, Palo Alto, CA (US); and Neelam Surana, Palaj (IN)
Assigned to Ceremorphic, Inc., San Jose, CA (US)
Filed by Ceremorphic, Inc., San Jose, CA (US)
Filed on Apr. 30, 2022, as Appl. No. 17/734,045.
Prior Publication US 2023/0352082 A1, Nov. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/408 (2006.01); G11C 11/4093 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4093 (2013.01); G11C 11/4094 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory device comprising:
a wordline controller configured to activate a wordline with a pulse width determined by one or more significant bits of an applied address in combination with at least two desired data error rates;
at least one memory array arranged as a sequence of columns of data, each column of data activated by an associated wordline, the activated wordline causing data from a column of memory cells associated with the wordline to be asserted to bitlines coupled to an input/output driver;
the wordline controller configured to cause an associated wordline pulse width to be longer for an address value which has a longer associated wordline than an address value which has a comparatively shorter associated wordline.