CPC G11C 11/4091 (2013.01) [H10B 12/09 (2023.02); H10B 12/50 (2023.02)] | 20 Claims |
1. A memory circuit, comprising:
a first memory array having a plurality of bit lines;
a second memory array having a plurality of bit lines;
a first sense amplifier connected to a first bit line of the first memory array and a first bit line of the second memory array; and
a second sense amplifier connected to a second bit line of the first memory array and a second bit line of the second memory array, the second bit line of the first memory array being adjacent to the first bit line of the first memory array, and the second bit line of the second memory array being adjacent to the first bit line of the second memory array, wherein the first bit line of the first memory array is displaced from the first bit line of the second memory array by a half pitch.
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