US 12,068,022 B2
Integrated circuit and memory device including sampling circuit
Woongrae Kim, Gyeonggi-do (KR); Byeong Yong Go, Gyeonggi-do (KR); Chul Moon Jung, Gyeonggi-do (KR); and Yoonna Oh, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Oct. 17, 2023, as Appl. No. 18/488,040.
Application 18/488,040 is a continuation of application No. 17/703,586, filed on Mar. 24, 2022, granted, now 11,823,730.
Claims priority of application No. 10-2021-0172410 (KR), filed on Dec. 3, 2021.
Prior Publication US 2024/0046977 A1, Feb. 8, 2024
Int. Cl. G11C 11/4076 (2006.01); G11C 11/406 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/4076 (2013.01) [G11C 11/406 (2013.01); G11C 11/4085 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first pattern generation circuit configured to generate a first pattern signal pulsing for a sampling section;
a second pattern generation circuit configured to generate a second pattern signal pulsing for the sampling section;
a first section control circuit configured to select one from a plurality of coarse sections of the sampling section, according to the first pattern signal;
a second section control circuit configured to select one from a plurality of fine sections of the sampling section, during the selected coarse section, according to the second pattern signal;
an output control circuit configured to generate a sampling enable signal based on the selected fine section; and
a sampling circuit configured to sample an input signal according to the sampling enable signal.