US 12,068,021 B2
Low power clock injection during idle mode operations
Noriaki Mochida, Yokohama (JP); Takayuki Miyamoto, Machida (JP); Kallol Mazumder, Dallas, TX (US); and Scott E. Smith, Plano, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on May 17, 2022, as Appl. No. 17/746,757.
Claims priority of provisional application 63/294,333, filed on Dec. 28, 2021.
Prior Publication US 2023/0206986 A1, Jun. 29, 2023
Int. Cl. G11C 11/4076 (2006.01); G11C 11/4093 (2006.01)
CPC G11C 11/4076 (2013.01) [G11C 11/4093 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an internal clock circuit configured to receive a first clock signal, a command to enter a low power mode, and an enable signal and to provide a second clock signal, wherein, in response to the command to enter the low power mode, the internal clock circuit is configured to intermittently enable and disable the second clock signal based on a duty cycle of the enable signal.