CPC G11C 11/4076 (2013.01) [G11C 11/4093 (2013.01)] | 21 Claims |
1. An apparatus comprising:
an internal clock circuit configured to receive a first clock signal, a command to enter a low power mode, and an enable signal and to provide a second clock signal, wherein, in response to the command to enter the low power mode, the internal clock circuit is configured to intermittently enable and disable the second clock signal based on a duty cycle of the enable signal.
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