US 12,068,018 B2
Power mode wake-up for memory on different power domains
Che-Ju Yeh, Kaoshiung (TW); Hau-Tai Shieh, Hsinchu (TW); and Yi-Tzu Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 4, 2023, as Appl. No. 18/230,461.
Application 18/230,461 is a continuation of application No. 17/824,260, filed on May 25, 2022, granted, now 11,763,873.
Application 17/824,260 is a continuation of application No. 17/103,294, filed on Nov. 24, 2020, granted, now 11,361,810, issued on Jun. 14, 2022.
Claims priority of provisional application 62/967,966, filed on Jan. 30, 2020.
Prior Publication US 2023/0395122 A1, Dec. 7, 2023
Int. Cl. G11C 11/4072 (2006.01); G11C 5/06 (2006.01); G11C 5/14 (2006.01); G11C 11/4074 (2006.01)
CPC G11C 11/4072 (2013.01) [G11C 5/06 (2013.01); G11C 5/14 (2013.01); G11C 11/4074 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory I/O system, comprising:
a first header circuit configured to receive a power supply voltage signal and having a first output terminal configured to provide a first output voltage signal in a first power domain to a first plurality of peripheral circuits;
a second header circuit configured to receive the power supply voltage signal and having a second output terminal configured to provide a second output voltage signal in a second power domain to a second plurality of peripheral circuits;
a control switch connected between the first and second header circuits, wherein when switching from a sleep mode to a wake-up mode, the control switch is configured to selectively provide the first output voltage signal in the first power domain to at least a portion of the second plurality of peripheral circuits without turning on the second header circuit.