US 12,068,014 B2
Semiconductor apparatus and method for manufacturing the same
Hiroyuki Uchida, Kanagawa (JP); and Yasuo Kanda, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 17/800,656
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
PCT Filed Feb. 11, 2021, PCT No. PCT/JP2021/005127
§ 371(c)(1), (2) Date Aug. 18, 2022,
PCT Pub. No. WO2021/186968, PCT Pub. Date Sep. 23, 2021.
Claims priority of application No. 2020-046220 (JP), filed on Mar. 17, 2020.
Prior Publication US 2023/0352070 A1, Nov. 2, 2023
Int. Cl. G11C 11/16 (2006.01); G11B 5/39 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01)
CPC G11C 11/161 (2013.01) [G11B 5/3912 (2013.01); G11C 11/1659 (2013.01); H10B 61/22 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor apparatus comprising a nonvolatile memory cell array including:
a plurality of first memory cells, each of the plurality of first memory cells including a first memory element including a resistance-variable nonvolatile memory element and a first selection transistor electrically connected to the first memory element, and
a plurality of second memory cells, each of the plurality of second memory cells including a second memory element including a resistance-variable nonvolatile memory element and a second selection transistor electrically connected to the second memory element, wherein
a plurality of first memory elements and a plurality of second memory elements are arranged in a two-dimensional matrix in a first direction and a second direction different from the first direction and on a same interlayer insulating layer,
the first memory element is larger than the second memory element, and
the first memory element and the second memory element are disposed adjacent to each other along the second direction.