CPC G09G 3/3233 (2013.01) [G09G 3/2007 (2013.01); G09G 2300/0852 (2013.01)] | 16 Claims |
1. A display panel, comprising a pixel driving circuit and a light-emitting device, wherein the pixel driving circuit comprises:
a first transistor, wherein the first transistor and the light-emitting device are series-connected between a first power line and a second power line, and the first transistor comprises a first electrode electrically connected to the first power line, a second electrode electrically connected to the second power line, and a gate electrically connected to a data line; and
a second transistor, wherein the second transistor and the light-emitting device are series-connected between the first power line and the second power line, and the second transistor comprises a first electrode electrically connected to the first power line, a second electrode electrically connected to the second power line, and a gate electrically connected to the data line;
wherein a width-to-length ratio of the first transistor is greater than a width-to-length ratio of the second transistor; the light-emitting device comprises a first sub-light-emitting device and a second sub-light-emitting device, the second electrode of the first transistor is electrically connected to the first sub-light-emitting device, and the second electrode of the second transistor is electrically connected to the second sub-light-emitting device;
the pixel driving circuit comprises a third transistor, a fourth transistor, a first capacitor, and a second capacitor, a first electrode of the third transistor is electrically connected to the data line, a second electrode of the third transistor is electrically connected to the gate of the first transistor, a gate of the third transistor is electrically connected to a scan line, a first electrode plate of the first capacitor is electrically connected to the gate of the first transistor, a second electrode plate of the first capacitor is connected to the second electrode of the first transistor, a first electrode of the fourth transistor is electrically connected to the data line, a second electrode of the fourth transistor is electrically connected to the gate of the second transistor, a gate of the fourth transistor is electrically connected to the scan line, a first electrode plate of the second capacitor is electrically connected to the gate of the second transistor, and a second electrode plate of the second capacitor is connected to the second electrode of the second transistor.
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