US 12,067,898 B2
Interactive environments using visual computing and immersive reality
Shao-Wen Yang, San Jose, CA (US); Addicam V. Sanjay, Gilbert, AZ (US); Karthik Veeramani, Hillsboro, OR (US); Gabriel L Silva, Phoenix, AZ (US); Marcos P. Da Silva, Chandler, AZ (US); Jose A. Avalos, Chandler, AZ (US); Stephen T. Palermo, Paradise Valley, AZ (US); Glen J. Anderson, Beaverton, OR (US); Meng Shi, Hillsboro, OR (US); Benjamin W. Bair, Hillsboro, OR (US); Pete A. Denman, Portland, OR (US); Reese L. Bowes, Hillsboro, AZ (US); Rebecca A. Chierichetti, Hillsboro, OR (US); Ankur Agrawal, Jaipur (IN); Mrutunjayya Mrutunjayya, Hillsboro, OR (US); Gerald A. Rogers, Chandler, AZ (US); Shih-Wei Roger Chien, Kaohsiung (TW); Lenitra M. Durham, Beaverton, OR (US); Giuseppe Raffa, Portland, OR (US); Irene Liew, Portland, OR (US); and Edwin Verplanke, Queen Creek, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 17/256,105
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Sep. 28, 2018, PCT No. PCT/US2018/053644
§ 371(c)(1), (2) Date Dec. 24, 2020,
PCT Pub. No. WO2020/068132, PCT Pub. Date Apr. 2, 2020.
Prior Publication US 2021/0272467 A1, Sep. 2, 2021
Int. Cl. G06F 9/38 (2018.01); G06F 9/455 (2018.01); G06T 19/00 (2011.01); G09B 5/06 (2006.01)
CPC G09B 5/067 (2013.01) [G06F 9/3877 (2013.01); G06F 9/45558 (2013.01); G06T 19/006 (2013.01); G06F 2009/45562 (2013.01); G06F 2009/4557 (2013.01); G06F 2009/45595 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computing device, comprising:
a physical network interface to communicate with a plurality of user devices over a network;
a main memory;
a processor comprising a processor cache and one or more processing cores, wherein the one or more processing cores are to execute a plurality of virtual machines, wherein the virtual machines are to establish a plurality of immersive reality sessions with the user devices and enable the immersive reality sessions to interact;
an accelerator circuit comprising:
an accelerator cache; and
a plurality of hardware accelerators, wherein the hardware accelerators comprise one or more infrastructure accelerators and one or more application accelerators; and
an interconnect to enable the processor and the accelerator circuit to share access to a coherent memory space, wherein the coherent memory space comprises the main memory, the processor cache, and the accelerator cache.