US 12,067,795 B2
Information processing device and information processing method
Yuki Yamamoto, Tokyo (JP); and Ryuta Satoh, Tokyo (JP)
Assigned to SONY GROUP CORPORATION, Tokyo (JP)
Appl. No. 17/440,194
Filed by Sony Group Corporation, Tokyo (JP)
PCT Filed Mar. 17, 2020, PCT No. PCT/JP2020/011600
§ 371(c)(1), (2) Date Sep. 17, 2021,
PCT Pub. No. WO2020/203240, PCT Pub. Date Oct. 8, 2020.
Claims priority of application No. 2019-068492 (JP), filed on Mar. 29, 2019.
Prior Publication US 2022/0012552 A1, Jan. 13, 2022
Int. Cl. G06V 30/00 (2022.01); G06V 30/194 (2022.01)
CPC G06V 30/194 (2022.01) 11 Claims
OG exemplary drawing
 
1. An information processing device comprising:
circuitry configured to
perform image recognition on an image of a predetermined number of images by a predetermined number of recognition processes, respectively, the predetermined number of the images being obtained by a predetermined number of terminals, the predetermined number of the terminals using a model that is updated by performing image recognition in each of the predetermined number of the terminals and executing unsupervised learning in each of the predetermined number of the terminals,
evaluate recognition results obtained in the predetermined number of the recognition processes, and
calculate an evaluation value for each of the predetermined number of the recognition processes,
wherein the learning is performed at timings with a predetermined interval at which each of the predetermined number of images is acquired in each of the predetermined number of terminals, respectively, and
wherein the circuitry is configured to calculate the evaluation value at a timing with a constant period that is longer than the predetermined interval.