US 12,067,642 B2
Memory latency-aware GPU architecture
Niti Madan, Santa Clara, CA (US); Michael L. Chu, Santa Clara, CA (US); and Ashwin Aji, Santa Clara, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Sep. 23, 2020, as Appl. No. 17/030,024.
Prior Publication US 2022/0092724 A1, Mar. 24, 2022
Int. Cl. G06T 15/00 (2011.01); G06F 3/06 (2006.01); G06F 9/50 (2006.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01)
CPC G06T 1/60 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0631 (2013.01); G06F 3/0679 (2013.01); G06F 9/5016 (2013.01); G06T 1/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least one processing unit; and
a resource manager circuit configured to selectively allocate a first memory portion or a second memory portion to the at least one processing unit based on application level memory access characteristics, wherein the first memory portion has a first latency that is lower than a second latency of the second memory portion.