US 12,067,472 B2
Defect resistant designs for location-sensitive neural network processor arrays
Rathinakumar Appuswamy, San Jose, CA (US); John V. Arthur, Mountain View, CA (US); Andrew S. Cassidy, San Jose, CA (US); Pallab Datta, San Jose, CA (US); Steven K. Esser, San Jose, CA (US); Myron D. Flickner, San Jose, CA (US); Jennifer Klamo, San Jose, CA (US); Dharmendra S. Modha, San Jose, CA (US); Hartmut Penner, San Jose, CA (US); Jun Sawada, Austin, TX (US); and Brian Taba, Cupertino, CA (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Mar. 30, 2018, as Appl. No. 15/942,298.
Prior Publication US 2019/0303741 A1, Oct. 3, 2019
Int. Cl. G06N 3/04 (2023.01); G06N 3/063 (2023.01)
CPC G06N 3/04 (2013.01) [G06N 3/063 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A system comprising:
a plurality of neural network processor cores arrayed in a grid, the grid having a plurality of rows and a plurality of columns; and
a network interconnecting at least those of the plurality of neural network processor cores that are adjacent within the grid, wherein:
the network comprises a switchable bypass between each adjacent core along each direction of two dimensions of the grid, each switchable bypass being directly connected, by a wire, to an input of one of the plurality of neural network processor cores and an output of that one of the plurality of neural network processor cores, and to an input of an adjacent one of the plurality of neural network processor cores, and
the network is adapted to bypass a defective core of the plurality of neural network processor cores by
applying the switchable bypass to provide a connection between two of the plurality of neural network processor cores in non-adjacent rows or columns of the grid, and
transparently routing messages between the two non-adjacent rows or columns, past the defective core, via the switchable bypass.