US 12,067,403 B2
Core mapping based on latency in a multiple core processor
Michael Christensen, Round Rock, TX (US); and Yuwei Cai, Pflugerville, TX (US)
Assigned to Dell Products L.P., Round Rock, TX (US)
Filed by Dell Products L.P., Round Rock, TX (US)
Filed on Jul. 22, 2022, as Appl. No. 17/871,078.
Prior Publication US 2024/0028344 A1, Jan. 25, 2024
Int. Cl. G06F 9/4401 (2018.01); G06F 9/38 (2018.01); G06F 9/46 (2006.01); G06F 12/02 (2006.01)
CPC G06F 9/4405 (2013.01) [G06F 9/3877 (2013.01); G06F 9/4403 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An information handling system, comprising:
a memory; and
a basic input/output system (BIOS) to communicate with the memory, the BIOS to:
receive a request to map a plurality of processor cores to a plurality of integrated memory controllers of a multiple core processor;
in response to the reception of the request, calculate a different latency for each of the plurality of processor cores;
based on the calculated different latency for each of the plurality of processor cores, assign mapping priority levels to the plurality of processor cores of the multiple core processor;
based on the mapping priority levels, map each of the plurality of processor cores to an associated one of the integrated memory controllers;
store the map of the plurality of processor cores in the memory; and
disable one or more of the plurality of processor cores based on the map of the plurality of processor cores and the calculated different latency for each of the plurality of processor cores.