| CPC G06F 9/3848 (2013.01) [G06F 9/3806 (2013.01); G06F 9/3844 (2013.01)] | 20 Claims |
|
1. A processor, comprising:
a fetch and decode circuit comprising:
a bias prediction circuit configured to predict, for a conditional instruction according to one or more previous executions of the conditional instruction, a bias prediction comprising a biased condition or an unbiased condition, wherein the biased condition indicates that a condition of the conditional instruction is always true or always false; and
an instruction prediction circuit configured to provide an instruction prediction for the conditional instruction;
wherein for an execution of the conditional instruction the fetch and decode circuit is configured to:
responsive to the bias prediction circuit predicting the biased condition for the execution of the conditional instruction:
determine a target address of the conditional instruction; and
bypass providing the instruction prediction for the conditional instruction by the instruction prediction circuit; and
responsive to the bias prediction circuit predicting the unbiased condition for the execution of the conditional instruction, provide, by the instruction prediction circuit, the instruction prediction for the conditional instruction;
wherein the bias prediction from the bias prediction circuit and the instruction prediction from the instruction prediction circuit are provided at different stages of processing of the conditional instruction in the fetch and decode circuit.
|