US 12,067,395 B2
Pre-staged instruction registers for variable length instruction set machine
Miles Robert Dooley, Austin, TX (US); Milos Trajkovic, Toronto (CA); Rakesh Shaji Lal, Toronto (CA); and Stanislav Sokorac, Austin, TX (US)
Assigned to Tenstorrent Inc., Toronto (CA)
Filed by Tenstorrent Inc., Toronto (CA)
Filed on Jan. 17, 2023, as Appl. No. 18/098,068.
Application 18/098,068 is a continuation in part of application No. 17/401,005, filed on Aug. 12, 2021, granted, now 11,599,358.
Prior Publication US 2023/0153110 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30145 (2013.01) [G06F 9/3004 (2013.01); G06F 9/30134 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A processor comprising:
a memory;
at least one functional processing unit;
a bus coupled to the memory;
a set of instruction registers coupled to the bus and storing a set of pre-staged instructions from the memory; and
a logic circuit coupled to the set of instruction registers and the at least one functional processing unit to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the memory.