	US 12,067,338 B2
	Multi version library cell handling and integrated circuit structures fabricated therefrom
Ranjith Kumar, Beaverton, OR (US); Quan Shi, Beaverton, OR (US); Mark T. Bohr, Aloha, OR (US); Andrew W. Yeoh, Portland, OR (US); Sourav Chakravarty, Portland, OR (US); Barbara A. Chappell, Portland, OR (US); and M. Clair Webb, North Logan, UT (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 26, 2022, as Appl. No. 17/585,101.
Application 17/585,101 is a division of application No. 16/629,802, granted, now 11,271,010, previously published as PCT/US2017/052584, filed on Sep. 20, 2017.
Prior Publication US 2022/0149075 A1, May 12, 2022
Int. Cl. G06F 30/392 (2020.01); G06F 30/20 (2020.01); G06F 30/337 (2020.01); G06F 30/347 (2020.01); G06F 30/373 (2020.01); G06F 30/3947 (2020.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01); H01L 27/118 (2006.01); H01L 27/00 (2006.01); H01L 27/11 (2006.01)

CPC G06F 30/392 (2020.01) [G06F 30/337 (2020.01); G06F 30/347 (2020.01); H01L 27/0207 (2013.01); H01L 27/0924 (2013.01); H01L 27/11807 (2013.01); G06F 30/20 (2020.01); G06F 30/373 (2020.01); G06F 30/3947 (2020.01); H01L 2027/11875 (2013.01)]

8 Claims

1. A method of fabricating a layout for an integrated circuit structure, the method comprising:

designating alternating ones of a plurality of gate lines parallel along a first direction as even (E) or odd (O) along a second direction;

selecting a location for a cell type over the plurality of gate lines;

selecting between a first version of the cell type and a second version of the cell type depending on the location, the second version structurally different than the first version, wherein the selected version of the cell type has an even (E) or odd (O) designation for interconnects at edges of the cell type along the second direction, and wherein the designation of the edges of the cell type match with the designation of individual ones of the plurality of gate lines below the interconnects.