US 12,067,283 B2
Memory apparatus and memory testing method thereof for correcting ROM code having error by ECC processing unit after determined to transition to safe mode
Makoto Senoo, Kanagawa (JP); and Katsutoshi Suito, Kanagawa (JP)
Assigned to Winbond Electronics Corp., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Jun. 28, 2022, as Appl. No. 17/851,041.
Claims priority of application No. 2021-107309 (JP), filed on Jun. 29, 2021.
Prior Publication US 2022/0413748 A1, Dec. 29, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0679 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An operation method of a semiconductor memory device, the semiconductor memory device comprising a controller that controls an operation based on a code read from a read-only memory, the controller comprising a cyclic redundancy check (CRC) processing unit, and the operation method comprising:
detecting whether a first code read from the read-only memory has an error by the CRC processing unit by using a first algorithm;
determining whether to transition to a safe mode by the controller when the CRC processing unit detects that the first code read from the read-only memory has the error; and
detecting and correcting the error of the first code detected by the CRC processing unit by an ECC processing unit after the controller determines to transition to the safe mode.