US 12,067,272 B2
Storage device and power management method thereof
Seung Hyun Chung, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jan. 14, 2022, as Appl. No. 17/576,660.
Claims priority of application No. 10-2021-0109094 (KR), filed on Aug. 18, 2021.
Prior Publication US 2023/0058022 A1, Feb. 23, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0634 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0625 (2013.01); G06F 3/0652 (2013.01); G06F 3/0679 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A storage device, comprising:
a plurality of memory devices configured to store peak power information including information about a plurality of peak power periods and information about identifications (IDs) respectively corresponding to one or more peak power periods among the plurality of peak power periods, the plurality of memory devices are coupled to a memory controller through one channel; and
the memory controller configured to assign a first ID among the IDs to a first memory device and a second memory device of the plurality of memory devices, provide a first memory operation command, instructing the first memory device to perform a first memory operation, to the first memory device through the one channel, and provide, while the first memory device performs the first memory operation, a second memory operation command, instructing the second memory device to perform a second memory operation, to the second memory device through the one channel,
wherein the first memory device starts the first memory operation at a first time, performs the first memory operation at peak power during a target period, corresponding to the first ID, among the plurality of peak power periods, and performs the first memory operation at power lower than the peak power during a non-peak period other than the target period, and
wherein the second memory device starts the second memory operation at a second time later than the first time, performs the second memory operation at the peak power during the target period, and performs the second memory operation at the power lower than the peak power during the non-peak period.