US 12,067,270 B2
Memory device security and row hammer mitigation
Yang Lu, Boise, ID (US); Sujeet Ayyapureddi, Boise, ID (US); Edmund J. Gieske, Boise, ID (US); Cagdas Dirik, Indianola, WA (US); Ameen D. Akel, Rancho Cordova, CA (US); Elliott C. Cooper-Balis, San Jose, CA (US); Amitava Majumdar, Boise, ID (US); Robert M. Walker, Raleigh, NC (US); and Danilo Caraccio, Milan (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 16, 2022, as Appl. No. 17/946,518.
Claims priority of provisional application 63/348,360, filed on Jun. 2, 2022.
Prior Publication US 2023/0393770 A1, Dec. 7, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0632 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a row activation command having a row address at control circuitry of a memory sub-system;
incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system;
determining, at the control circuitry, whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC), wherein the second count is incremented each time the CAM is full; and
responsive to determining that the first count is greater than the RHT minus the second count, issuing a refresh command to the row address.